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-1 6.92882 7.8933 vertex 1 6.37595 12.8553 vertex 1 5.78941 6.73694 vertex -0.95 0 22.5 vertex 0.95 0 22.5 vertex 0.95 4.22131 20.5 vertex -0.95 7.77656 6.96334 vertex -0.95 0 22.5 vertex -0.95 7.77656 6.96334 vertex -0.95 6.11494 21.5472 vertex 0.95 0 22.5 vertex 0.95 5.78941 6.73694 vertex -1 5.39134 21.8333 facet normal 0.900364 0.423669 0.099239 facet normal 4.720716e-001 -8.093081e-001 3.495267e-001 vertex -3.443231e+000 2.638496e+000 2.480400e+001 facet normal -2.845742e-001 -4.980054e-001 8.191509e-001 facet normal -7.990003e-01 -6.013306e-01 -3.235123e-04 vertex -9.176074e+01 9.441686e+01 1.855000e+01 vertex -9.698088e+01 9.171996e+01 2.655000e+01 facet normal 8.724512e-001 3.884962e-003 4.886858e-001 facet normal 5.555843e-01 -8.314602e-01 -3.414617e-04 vertex -9.355745e+01 9.281117e+01 3.455000e+01 vertex -1.034745e+02 9.507449e+01 1.055000e+01 facet normal -1.90074e-06 -0.995049 0.0993842 facet normal -8.452844e-01 0.000000e+00 5.343166e-01 facet normal -8.314790e-01 5.555561e-01 -1.894494e-04 facet normal -7.865136e-14 -1.000000e+00 -3.499570e-14 facet normal -0.991524 -0.109222 -0.0703609 vertex 4.76941 -8.07987 6.03331 facet normal -2.304122e-004 -4.032215e-004 -9.999999e-001 Latest commits for file Images/capsocket.png b554ec2138 Add footprint items for panel holes; separate panel and pcb into different files Add a front-panel PCB Add a front-panel PCB More tweaks after pro review "extra_units": "error", "global_label_dangling": "warning", "hier_label_mismatch": "error", "label_dangling": "error", "lib_symbol_issues": "warning", More tweaks after pro review } ], "meta": { "version": 3 }, "net_colors": null, "netclass_assignments": null, updates to rev 2 beta by adding +5V, and both trigger/gate and CV routing updates led holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf 25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm.

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