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BackPin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_6_3.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py XDFN4 footprint (as found on the left sub-panel right_rib_x = width_mm - thickness*2.2; footprint "SLIDE_POT_0547" (version 20221018) (generator pcbnew footprint "POT_2_PIN_Header" (version 20211014) (generator pcbnew footprint "SOCKET_2_PIN_Header" (version 20211014) (generator pcbnew 9f9f6acf76 Add notes about wiring SW15 cross-board UI: 11 potentiometers 11 SPDT switches 1 rotary switch, 5+ positions 6 sockets Potentiometers: One potentiometer for internal clock rate. One SPDT switch to adjust CV output range, switch between 5v and 2.5v max. One per step, to enable/disable gate per step. (10 One potentiometer for internal clock rate. One potentiometer for internal clock rate. Arrasta Playbook REP: repique CAX: caixa MSD: mid surdo (sometimes MS1, MS2, etc, if pattern spans measures or variations) BSD: back surdo (L for low, H for high R/L: accented note (right/left hand suggested)