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BackLayer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes Total unplated holes count 16 ============================================================= Total unplated holes count 16 ============================================================= Total unplated holes count 0 Minor layout tweaks Schematics/Fireball_VCO.pdf | Bin 38764 -> 0 bytes From b2f0340111348a8deafde0ffe244939fe4eeb6b7 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Use THT electrolytics, finish SMT layout, try on quentin font for size Compare 2 commits » merged pull request 'Finish schematic, add PDF' (#2) from schematic by Eeschema 5.1.10-88a1d61d58~90~ubuntu20.04.1 **Component Count:** 76 | Refs | Qty | Component | Description | Vendor | SKU | | | S2 | 1 | B10k | **Potentiometer, 9 mm vertical board mount OR: | | C3, C4, C5 | 3 | AudioJack2 | Audio Jack, 2 Poles (Mono / TS) | | S2 | 1 | LED | Light emitting diode | | | | | | | | J3 | 1 | TL074 | Quad Low-Noise JFET-Input Operational Amplifiers, DIP-8/SOIC-8/TO-99-8"/>