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Normal 0.268415 -0.834578 0.481075 facet normal -0.946356 -0.3075 0.0992725 facet normal -0.584885 -0.80502 0.0992537 facet normal -0.880757 -0.468313 -0.0703594 vertex 2.34079 9.54557 1.52757 vertex 2.11143 -9.25077 6.17306 vertex -0.709089 -9.46214 6.17306 vertex 5.05426 -8.44501 1.45229 facet normal -0.705398 0.0694843 0.705398 0.705398 vertex 9.71631 -0.301613 3.26879 facet normal -7.808608e-001 -2.020115e-003 6.247017e-001 vertex -5.948193e-001 -4.413863e+000 2.488700e+001 facet normal -0.0729258 0.976256 0.203976 facet normal 9.290075e-01 -1.163247e-03 3.700590e-01 vertex -1.081833e+02 9.725134e+01 4.734130e+00 facet normal -0.116041 -0.000467445 0.993244 vertex 6.9148 -0.996058 7.89166 facet normal 0.980785 0.195093 -6.7267e-08 vertex -3.16821 -1.29095 18.1498 facet normal 0.0611117 0.0769646 -0.995159 vertex 5.35771 -8.43833 0.0434047 facet normal 0.100994 -0.992167 0.0735183 vertex 4.24331 2.97557 21.7998 vertex 4.94225 -0.762348 21.7809 facet normal 0.55474 -0.0546157 0.830229 facet normal 0.499992 -0.86603 -1.51289e-06 facet normal -9.449638e-01 6.305657e-04 -3.271744e-01 vertex -1.084626e+02 9.695134e+01 1.068604e+01 facet normal -0.0979878 -0.988483 0.115323 facet normal 0.0342449 -0.29048 0.956268 facet normal 5.362037e-14 -1.000000e+00 2.260962e-15 facet normal -4.203270e-16 -1.856182e-15 -1.000000e+00 facet normal 0.265121 -0.618898 0.739376 facet normal 0.000000e+00 -1.000000e+00 1.134057e-06 facet normal 0.499812 0.866134 -0.000277976 facet normal -0.388724 0.815359 0.429049 facet normal -0.309927 0.7481 0.586763 vertex 3.2761 -2.20578 19.9 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf * [How to use](Docs/use.md 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 63579cf959 Add notes about UX component wiring 9f9f6acf76f746b4755da71c07bb656091774052 SMT updates SMT updates Checkpoint after converting most things to SMD Latest commits for branch new_footprints Final revision; added custom DRC as project file tstamp a19ef654-a631-44b9-8b6b-999333495c1b) Final revision; added custom DRC as project file new_footprints Added hard sync input. CV in controls the clock 3c7abf2196 Go to file 55ee65a5e9 Checkpoint after fixes but before shrinking boards Merge issues to be a 13-roll, but when starting they only play the last step and output CV continously while paused. Sequencer cascading to trigger a second sequencer's run, which then re-triggers the first. More feature ideas: Trigger out - Gate out, with probably +12v gates. Variable step count, 1-10 steps possible (with 2-3 extra switch positions to re-use for frequently-swapped positions). - External reset via momentary push button. Play continuously or play once (switch to select segments from each step. Could add a switch to disable reset (run once). - Momentary-normal-off pushbutton to manually reset. LEDs: One per step, to enable/disable gate per step. (10 - One potentiometer for internal clock signal (possibly external). Commonly called a "Baby 8". Final tweaks, version.

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