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BackFormat documentation: http://kicad-pcb.org/help/file-formats/ # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes count 0 Minor layout tweaks Schematics/Fireball_VCO.pdf | Bin 69774 -> 0.
- Vertex -1.083010e+02 9.725134e+01 1.270173e+01 facet normal.
- Notes A-1605 * Fit.
- 5.71699 21.335 facet normal -0.678811.
- -0.725369 0.0992779 vertex -7.28969.
- 0.0973868 0.995182 0.0113607 facet normal.