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Back: F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: merged pull request 'pcb_finalization' (#1) from pcb_finalization into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/2 From 972d8b1e0797912e848110b19e1af10ed411bbbb Mon Sep 17 00:00:00 2001 Subject: [PATCH] Submodules.
- -1.090719e+02 9.725134e+01 1.214754e+01 facet normal.
- 0.754473 0.0703595 vertex 9.05498 -4.46195 0.0491304.