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Easy hole_bottom = hole_top - 89.75; hole_right = hole_left + 78.5; 0d370a24cd Add VCA shaek layout 0d370a24cdcaf6d3fd7f0316855522b79df0fe9a 3583986e89 Finished PCB, passes all passable DRCs created pull request 'More schematics' (#3) from schematic by Eeschema 5.1.9-73d0e3b20d~88~ubuntu20.04.1 Generated from schematic into main ... Finish schematic, add PDF Features already done: - Internal clock with manual control. Clock in socket with amplifier to handle weaker (<6v) signals Sequencer cascading to trigger a second sequencer's run, which then re-triggers the first. CV.

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