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Back[ ord*cos(lf2), ord*sin(lf2), h0], [ ird*cos(lf0), ird*sin(lf0), h1], [ ird*cos(lf2), ird*sin(lf2), h1], [ 0,0,h2], Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes Total unplated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes: ============================================================= 2bd01a1ff2d30ca3cff647bbf3b80645437cc07c Add schematic, start on PCB Fireball/Fireball.kicad_sch | 64 Fireball/fp-info-cache | 9 create mode 100644 Hardware/Panel/precadsr_panel.svg create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/SOT-23_Handsoldering.kicad_mod delete mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/OSHW-Logo2_7.3x6mm_SilkScreen.kicad_mod create mode 100644 Hardware/Panel/precadsr_panel_al/fp-lib-table create mode 100644 Hardware/Panel/precadsr_panel_al/precadsr_panel_al.pro create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Power_Header.kicad_mod create mode 100755 Panels/FireballSpell_Large.webp create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/C_Disc_D3.0mm_W1.6mm_P2.50mm.kicad_mod create mode 100755 PSU/PSU.md main MK_VCO/Fireball/Fireball.kicad_pro 505 lines | Refs | Qty | Component | Description | Manufacturer | Part | Vendor | SKU | | | | | L1 | 1 | 10R | Resistor | | | | | | | | | C2, C5, C6, C8, C9 Schottky Barrier Rectifier Diode, DO-41 D3, D4, D5, D8, D9, D10 | 8 create mode 100644 Schematics/SynthMages.pretty/Switch.lib create mode 100644 Hardware/PCB/precadsr_Gerbers/precadsr-F_SilkS.gbr create mode 100644 3D.
- HLE-147-02-xx-DV-TE, 47 Pins per row (https://www.molex.com/pdm_docs/sd/874371443_sd.pdf#page=2 molex pico.
- ESOP-12B SMT Flat Package with Heatsink Tab.