Update luther's layout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= f51b7b97734e404127fa5d5d263acbfd66f116e4 Add schematic, start on PCB with exploratory 8hp layout 0d370a24cdcaf6d3fd7f0316855522b79df0fe9a 3583986e89 Finished PCB, passes all passable DRCs Show-stopping bugs needing bodges: Errant connection between R25 and R1. This needs to be larger than the Dailywell SPDT. | R31 | 1 | 10nF | Film capacitor | | Tayda | A-559 | | | | | | | L1 | 1 | 1 | ICM7555xP | CMOS General Purpose Timer, 555 compatible, PDIP-8"/> Small Signal NPN Transistor, TO-92 Audio Jack, 2 Poles (Mono / TS *(optional) SIP socket, 2.54 mm, 1x7 Pin socket, 2.54 mm, 1x10.
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