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BackNotes cb59d1e9c06865f5bebe8c7ee0afa4859e0766b2 Update Schematics/schematic_bugs_v1.md Clock POT is too small for a little bit of margin // margins from edges v_margin = hole_dist_top*2 + thickness; v_margin = hole_dist_top*2 + thickness; v_margin = hole_dist_top*5.
- 1.056975e+02 4.255000e+01 facet normal.
- 9774090982 (https://katalog.we-online.de/em/datasheet/9774090982.pdf), generated with kicad-footprint-generator Resistor.
- 3x3mm Pitch 0.5mm right.