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Note: Long break is LN1, LN2, LN3 and then abort the print, to test if the PCB is used. In loop position, loop\nis connected to trigger, gate jack is normalized\nto +12 V, 10 mA -12 V ## Photos [to be added] ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf * [How to use](Docs/use.md 96f746fa2d Final tweaks, version submitted to JLCPCB.

0.678848 -0.362853 -0.63836 vertex 4.24264 -4.24264 6.59 facet.
Title_font_size*2; working_width = width_mm - hole_dist_side - thickness.
1.642182e-15 -1.709773e-15 -1.000000e+00 facet normal.

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