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BackClose Testing before powering up: Clock In Normal - 1k to U2-8 (AND NOT short to U2-10 - Clock rate goes down when resistance goes up, opposite to expectation. C1 is too small for film; is film needed? More notes Schematics/schematic_bugs_v1.txt | 2 Latest commits for branch bugfix/triangle_smoothness Add note resulting from real TL0x4s d12ec1f19bbae8f01395e4c76a152d3d4ce7a3d4 More repo cleanup, adopt github .gitignore file ad96459571a569a983e452184e49702fe8779c4e Merge pull request 'Fix rail clearance issues, add PCB slot, more options for potentiometer spoke placement Fix rail clearance issues, make all power traces large "rules": { PCB initial layout, no traces "min_copper_edge_clearance": 0.0, PCB initial.
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