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Shrinking boards Checkpoint after tweaking footprints some more, starting over at 14hp PCB initial layout, no traces Initial kicad, images, gitignore for kicad backups afea9d5a2c Final revision; added custom DRC as project file tstamp 60305f7c-b08f-48d5-a3e4-4d4a9046f92f) Final revision; added custom DRC as project file (pts Final revision; added custom DRC as project file (pts Final revision; added custom DRC as project file (pts Final revision; added custom DRC as project file ) ) Latest commits for branch.

Http://www.latticesemi.com/view_document?document_id=213 Lattice caBGA-756, ECP5 FPGAs.
9.924497e-001 facet normal -0.0243222.
Front Panel v2.kicad_pcb Normal file.
S06B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator.

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