3
1
Back

Back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes: merged pull request 'More schematics' (#3) from schematic by Eeschema 5.1.10-88a1d61d58~88~ubuntu20.04.1 **Component Count:** 76 | Refs | Qty | Component | Description | Manufacturer | Part | Vendor | SKU | | | Screws, nuts, and spacers (see build notes) 1 SIP socket, 2.54 mm, 1x7 | | | J3, J4, J5 | 3 | 10k | Resistor | | | J5, J12, J13 | 3.

New Pull Request