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Middle PCB checkpoint after roughing out middle PCB ebf8c2dd87 Move LED resistors next to transistors to wide

Change page size to 9mm and align it precisely for repeatability Change transistor footprint to inline_wide, fix DRC ground plane Latest commits for file caixa_sr1.png Image of caxia score Image of caxia score 531ebcae92 Add html test version b1fcba1e78f37669542b35a3e32a5257c5c0240c f51b7b97734e404127fa5d5d263acbfd66f116e4 Add schematic, start on PCB sandwich, making some final-ish decisions about connecting to front panel 24ca7abc85681936397a2802c8155420fcaf679c updated C14 footprint, traces, groundplane 82024e96c9b263a83b6caf715e8607e9cf1b7d77 updated README.md updated README.md 8fe829edc2a52299443ce1d2193e2aa04d060c17 From b22080a808f5ee5eddd0b607f432f7fa2c4fb139 Mon Sep 17 00:00:00 2001 Subject: [PATCH 06/13] add pic Schematics/bad_trace_v1.jpeg | Bin 0 -> 15005 bytes Panels/FireballSpellVertVerySmall.png | Bin 0 -> 317907 bytes Images/PXL_20210831_004139245.jpg | Bin 0 -> 26933738 bytes SNARE_MANUAL.pdf | Bin 0 -> 16369 bytes main MK_SEQ/Schematics/schematic_bugs_v1.md 48 lines main MK_SEQ/Schematics/notes.txt 35 lines Binary files /dev/null and b/Images/precadsr-panel-art.png differ Binary files a/3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/PRISMATIC SPHERE.png' 9bb3093b2b Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/POLYMORPH.png' Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/COLOR SPRAY.png differ Binary files /dev/null and b/3D Printing/Rails/18hp_innie.stl differ Binary files.

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