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BackHoles Total unplated holes count 16 Not plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes Total unplated holes count 0 Minor layout tweaks merged pull request 'new_footprints' (#5) from new_footprints into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/4 Put title box in PDF export' (#4) from schematic by Eeschema 5.1.10-88a1d61d58~90~ubuntu20.04.1 **Component Count:** 74 **Component Count:** 76 | Refs | Qty | Component | Description.
- Dual, http://www.taiwanalpha.com.tw/downloads?target=products&id=113 potentiometer vertical 9mm.
- 4.929500e-001 8.620432e-001 1.178210e-001 facet normal -0.555576 -0.831466 -1.03191e-06.
- HLE-112-02-xxx-DV-A, 12 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated.
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Num="7" name="V+" type="power_in"/>
- -4.349519e+000 2.475471e+001 facet normal 0.796859 -0.175921 0.577986 vertex.