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Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= d9153c70802a10d2fe554f80f1a497b409aac630 0d3d72c49e606725216a5a9a4217e6c039d5a574 2dd0b8c0c736720a0b064bbe1304dc9562beb260 Latest commits for branch pcb_finalization re-re-remove the mysterious extra trace .../Unseen Servant/Unseen Servant.kicad_sch | 30 .../precadsr_aux_Gerbers/precadsr-F_Mask.gbr | 185 .../precadsr_aux_Gerbers/precadsr-B_Paste.gbr | 4 | 1M | Resistor | | | | | J1 | 1 | Conn_01x02 | SIP socket, 2.54 mm, 1x2 (see [build notes](build.md | | Tayda | A-1135 | | | | | | .

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