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Back5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes Total unplated holes count 16 Not plated through holes: unplated through holes: merged pull request synth_mages/MK_VCO#5 Final revision; added custom DRC as project file Final revision; added custom DRC as project file 33729ec97f6dd2ed68c4ca06088ce0b21651948d Align panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability b11a8d31874f2e074879a668b4f6eb5f32915bd6 Change transistor footprint to inline_wide, fix DRC ground plane 5e32fb4fc0953f2a10f8dc9cf7a0a3653bcbf4f2 @circuitlocution.com created pull request synth_mages/MK_VCO#5 613d1b6f7e.
- 5.10452 0.896427 21.7998 facet normal 0.847874 -0.479685.
- 112.805 (end 170.76005 108.25 (end 173 103.541823.
- Connector, 07 bottom-side contacts, 1.0mm pitch, 1.0mm height.
- -0.4 -3.34543 18.1498 facet normal.
- 19.9417 facet normal -0.481758 -0.876304 0.