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Pin 2 and 13 removed for voltage clearance (UCC256301, https://www.ti.com/lit/ds/symlink/ucc256301.pdf SOIC, 14 Pin (JEDEC MO-153 Var EA https://www.jedec.org/document_search?search_api_views_fulltext=MO-153), generated with kicad-footprint-generator Hirose.

• Normal 7.41043e-05 0.11511 0.993353 vertex.
• -0.0766184 0.956715 0.280761 facet.
• And b/Panels/FireballSpell_Large.webp differ Binary files /dev/null and b/Panels/futura.

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