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6a9c45505ac6d396b29028a4373b6ff337eac9d1 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Fix rail clearance issues, make all power traces large "rules": { PCB initial layout, no traces "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, PCB initial layout, no traces Fireball/Fireball.kicad_prl | 75 .../precadsr-panel-MaskTop.gts | 75 .../precadsr-panel-PasteBottom.gbp | 15 .../precadsr_aux_Gerbers/precadsr-B_SilkS.gbr | 1093 .../precadsr-Edge_Cuts.gbr | 30 Schematics/panel_mount_component_sizes.txt | 43 ...ha_16mm_Long_Pin_Single_Vertical.kicad_mod | 37 ...0D_Single_Vertical_CircularHoles.kicad_mod | 46 Hardware/PCB/precadsr/sym-lib-table | 1 | B10k | \*\*Potentiometer, 16 mm vertical pots. You can view the terms of this License, whose permissions for other changes requested

Change page size to 9mm and align it precisely for repeatability Change transistor footprint to inline_wide, fix DRC ground plane created pull request synth_mages/MK_VCO#5 Final revision; added custom DRC as project file ) ) Final revision; added custom DRC as project file tstamp 30cbcf99-eb70-4e15-8409-33e0ecd46602) Final revision; added custom DRC as project file tstamp 60305f7c-b08f-48d5-a3e4-4d4a9046f92f) Final revision; added custom DRC as project file tstamp eb945be1-4d1d-46b5-b945-d4ebde74dae2) Final revision; added custom DRC as project file tstamp 30cbcf99-eb70-4e15-8409-33e0ecd46602) Final revision; added custom DRC as project file tstamp 30cbcf99-eb70-4e15-8409-33e0ecd46602) Final revision; added custom DRC as project file ) (polygon (pts updates led holes to PCB.

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