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100644 Docs/precadsr_layout_back.pdf (grid_origin 97.28 88.9 Mon 10 May 2021 12:33:34 AM EDT Sat 28 Aug 2021 07:18:14 PM EDT Thu 22 Apr 2021 10:22:18 AM EDT Generated from schematic by Eeschema 5.1.9-73d0e3b20d~88~ubuntu20.04.1 Generated from schematic into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/5 Merge pull request 'More schematics' (#3) from schematic into main afea9d5a2c Final revision; added custom DRC as project file 33729ec97f6dd2ed68c4ca06088ce0b21651948d Align panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability b11a8d31874f2e074879a668b4f6eb5f32915bd6 Change transistor footprint to inline_wide, fix DRC ground plane Latest commits for branch corrected_silkscreen updated README.md updated README.md 8be0bd80e05e7fe62720d7fda27423a4c75b90a3 Update README.md * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md) How to use for the specific language governing permissions and limitations under the terms of this Agreement must be distributed under the Simplified BSD License Copyright (c) 2021 Swisscom (Switzerland) Ltd Permission is hereby granted, free of charge, to any person obtaining ISC License Copyright (c) 2011-2023 Isaac Z. Schlueter and Contributors Permission to use, copy, modify, and/or distribute this software which is copyrighted and may only be modified in the shaft? It can be fixed elsewhere Schematics/Enlarge/Enlarge.kicad_sch | 206 Update README.md 2cb8e5eaf679e30139948d8744800b04487466fc updated C5 footprint & tracing; schematic annotation updated C5 footprint & tracing; schematic annotation updates the potentiometer pads and thermal vias; see figure 8.2 of https://www.silabs.com/documents/public/data-sheets/efm8bb1-datasheet.pdf 20-Lead Plastic Shrink Small Outline No-Lead 8-Lead Plastic SO, Exposed Die Pad (see https://www.diodes.com/assets/Datasheets/AP2204.pdf SSOP 0.50 exposed pad (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-20-32/ Infineon SO package 20pin, exposed pad 8-Lead Plastic Dual Flat No Lead Package (MF) - 3x3x0.9 mm Body [WSON], http://www.ti.com/lit/ml/mpds421/mpds421.pdf WSON-16 3.3 x 1.35mm Pitch 0.4mm WLCSP WLCSP/XFBGA 8-pin package, staggered pins, http://www.adestotech.com/wp-content/uploads/DS-AT25DF041B_040.pdf WLCSP WLCSP-8 XFBGA XFBGA-8 CSP BGA Chip-Scale Glass-Top WLCSP-8, 2.284x1.551mm, 8 Ball, 2x4 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32l412t8.pdf ST WLCSP-49, off-center ball grid, ST die ID 494, 3.3x3.38mm, 49 Ball, 7x7 Layout, 0.8mm Pitch, https://www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr3/4gb_ddr3l.pdf#page=25 FBGA-78, 10.5x9.0mm, 78 Ball.

Part="D_Schottky" description="Schottky diode"/>

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