synth_tools

Back

Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: unplated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole Total plated holes count 0 Minor layout tweaks Schematics/Fireball_VCO.pdf | Bin 0 -> 11692 bytes .../HOLD PORTAL.png | Bin 69774 -> 0 bytes Latest commits for file Images/befaco_vcadsr.png Add befaco image for inspo Compare 15 commits » created pull request 'More schematics' (#3) from schematic into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/4 Put title box in PDF export' (#4) from schematic into main 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 Final tweaks, version submitted to JLCPCB on 20240124 Experimenting with more panel layout Initial stab at a charge no more than 100k to get below 200bpm~ From a5c5ff12ce18fecaaf346f973863d12bf361ac82 Mon Sep 17.

New Pull Request

Labels Milestones