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Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: merged pull request synth_mages/MK_SEQ#2 b77534e3fc Added schmancy pcb for v1 build - C1 is too small; need more than 100k to get 1:1 between schematic and PCB, no warnings schematic start, and some example modules main 5a4e89eea6 Add position for resistor between coarse and fine pitch, FM level, pulse wave width, and PWM level.

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