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(see https://www.intersil.com/content/dam/Intersil/documents/l72_/l72.10x10c.pdf LFCSP VQ, 48 pin, exposed pad, thermal vias, http://www.ti.com/lit/ds/symlink/drv8870.pdf 20-Pin Thermally Enhanced Thin Shrink Small Outline (SS)-5.30 mm Body [SOIC], see https://ac-dc.power.com/sites/default/files/product-docs/senzero_family_datasheet.pdf Power-Integrations variant of 10-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils 14-lead surface-mounted (SMD) DIP package, row spacing 10.16 mm (400 mils), Socket.

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