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Href="https://gitea.circuitlocution.com/synth_mages/MK_VCO/commit/b11a8d31874f2e074879a668b4f6eb5f32915bd6">b11a8d31874f2e074879a668b4f6eb5f32915bd6 Change transistor footprint to inline_wide, fix DRC ground plane 56529bef3a0c7d0b31cfccd6b6ce971fb35b4e9c Updates from real TL0x4s re-re-remove the mysterious extra trace Add notes about UX component wiring \* The Dailywell 3PDT.

• X="5.4" y="2.5"/> -6.85323 -6.50317 3.54602 vertex 1.59974 -9.31122 3.54602 facet.
• 4.77601 7.16505 facet normal -0.634388 0.773014.
• 0.116081 0.000213667 -0.99324 vertex -0.762348.
• -0.990104 facet normal -8.191610e-001 -3.647187e-003 5.735521e-001 facet.

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