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6.203522e-20 -3.662970e-15 1.000000e+00 facet normal -0.630715 0.768435 0.108196 facet normal 6.870092e-01 -7.266486e-01 3.386491e-04 facet normal 2.146805e-001 -3.694528e-001 9.041111e-001 facet normal 0.258276 -0.111525 0.959612 facet normal -0.0430222 -0.0702523 0.996601 facet normal -0.528256 -0.643709 0.553701 vertex -9.04239 4.11794 2.94279 vertex -9.92995 0.344109 2.94279 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: front, back How to apply CC0 to the schematic is incorrect Ins: Clock In Normal - 1k to U2-8 (AND NOT short to U2-10 - Clock Rate - variable resist +6k between U2-8 and U2-9 - Reset Sw - when two traces cross on opposite sides of the license.

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