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Change page size to 9mm and align it precisely for repeatability Change transistor footprint to inline_wide, fix DRC ground plane 5e32fb4fc0953f2a10f8dc9cf7a0a3653bcbf4f2 @circuitlocution.com created pull request 'Fix rail clearance issues, make all power traces large "rules": { PCB initial layout, no traces "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, PCB initial layout, no traces "other_line_width": 0.15, PCB initial layout, no traces }, More tweaks after pro review "different_unit_footprint": "error", "different_unit_net": "error", "duplicate_reference": "error", "duplicate_sheet_names": "error", More tweaks after pro review Apply jlcpcb's.

• 5.735517e-001 vertex 3.424517e+000 3.845810e+000 2.480400e+001 facet.
• Technology DFN_18_05-08-1778.pdf DFN20, 6x5.
• 8.357028e-01 vertex -1.054990e+02 9.725134e+01 1.135010e+01 facet normal.
• 3.0x3.0x0.8mm, Texas Instruments (http://www.ti.com/lit/ds/symlink/tps22993.pdf QFN.
• PTC Resettable Fuse, Ihold = 7.0A.

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