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BackLayout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes count 0 Minor layout tweaks Based on designs from: Skull & Circuits (https://www.skullandcircuits.com/vca-1-2/ Moritz Klein (https://www.ericasynths.lv/shop/diy-kits-1/edu-diy-vca/ Two voltage-controlled amplifiers Latest commits for file Fireball/Fireball.kicad_dru main synth_tools/Schematics/SynthMages.pretty/SLIDE_POT_0547.kicad_mod 84 lines tstamp a4699170-083b-499a-bdb3-b2682e117d7f) ) Schematic updates create mode 100644 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-drl_map.pdf create mode 100644 Docs/use.md create mode 160000 Kosmo_panel Subject: [PATCH] traces added but maybe won't keep main synth_tools/Schematics/SynthMages.pretty/Perfboard_4x12.kicad_mod 86 lines From b92fcb7c680efef9f394f5f872d087549294e6cf Mon Sep 17 00:00:00 2001 Subject: [PATCH] KiCad 6, update symbols Latest commits for file Envelope/Envelope.kicad_pro Latest commits for file Panels/QuentinEF.ttf PSU/Synth Mages Power Word Stun.kicad_prl | 4 | 100 nF | Unpolarized capacitor | | | Tayda | A-1672 | | | | C2, C5, C6, C8, C9 Schottky Barrier Rectifier Diode, DO-41"/>
- -0.435833 0.815355 0.38111 vertex -9.04239 -4.11794.
- Strip, HLE-147-02-xxx-DV-BE-LC, 47 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated.