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Back'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 ============================================================= Total unplated holes count 0 Minor layout tweaks merged pull request 'Finish schematic, add PDF' (#2) from schematic into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/3 Merge pull request synth_mages/MK_VCO#5 Final revision; added custom DRC as project file Add jlc constraints DRC; replace order number text Fireball/Fireball_panel.kicad_pcb | 3 | 2_pin_Molex_header | 2 | 1N5817 | Schottky diode | | | | | C2, C5, C6, C8, C9 | 5.
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