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Pitch, https://www.dialog-semiconductor.com/sites/default/files/da1469x_datasheet_3v1.pdf#page=740 VFBGA-100, 10x10, 7x7mm package, pitch 0.4mm; see section 7.2 of http://www.st.com/resource/en/datasheet/stm32f378vc.pdf WLCSP-72, 9x9 raster, 4.4084x3.7594mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32l152zc.pdf UFBGA 132 Pins, 0.5mm Pitch, http://www.ti.com/lit/ds/symlink/txb0104.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf BGA 12 0.5 R-XBGA-N12 Texas Instruments, DSBGA, 1.4715x1.4715mm, 9 bump 3x3 (perimeter) array, NSMD pad definition Appendix A BGA 1156 1 FF1157 FFG1157 FFV1157 FF1158 FFG1158 FFV1158 Virtex-7 BGA, 44x44 grid, 45x45mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=278, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=92, NSMD pad definition (http://www.ti.com/lit/ds/symlink/txs0104e.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf Texas Instruments BGA-289, 0.4mm pad, based on the cylindrical edge of the rail + a safety margin center_adjust = 2.5; //mm first_col = 10.1+center_adjust; //mm second_col = width_mm/2; vertical_space = height * rotate_vector_cos; points = [ [left_edge, rotate_vector_cos * rail_depth], // top horizontal rib h_wall(h=4, l=right_rib_x); // middle-bottom h rib h_wall(h=1.6, l=right_rib_x); // middle horizontal rib // h_wall(h=1.6, l=right_rib_x); // bottom right [right_edge, rotate_vector_sin * height], // top point? .

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