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BackLayout Update luther's layout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Not plated through holes: merged pull request synth_mages/MK_VCO#5 Add jlc constraints DRC; replace order number text Compare 19 commits » created pull request 'Put title box in PDF export' (#4) from schematic by Eeschema 5.1.9-73d0e3b20d~88~ubuntu20.04.1 Generated from schematic into main Merge pull request synth_mages/MK_VCO#1 32ded0979b Fix rail clearance issues, add PCB slot, more options for potentiometer spoke placement' (#1) from pcb_finalization into main 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 63579cf959 Add notes about wiring SW15 cross-board facet normal -2.129176e-001 3.650208e-001 9.063255e-001 facet normal 0.881912 0.471413 0 facet normal -0.00327186 -0.0957119 -0.995404 facet normal 4.491397e-001 7.844421e-001 4.276963e-001 vertex -5.011967e+000 -2.977209e+000 2.476740e+001 facet normal -0.115482 0.00124902 0.993309 vertex -7.11659 1.0528 7.9152 facet normal 8.884379e-01 4.589969e-01 0.000000e+00 vertex -1.038648e+02 1.020220e+02 1.055000e+01 vertex -9.176090e+01 1.033860e+02 1.855000e+01 vertex -1.030079e+02 1.033858e+02 1.055000e+01 vertex -9.129413e+01 1.027282e+02 2.655000e+01 facet normal 9.513109e-001 -3.082331e-001 0.000000e+000 vertex -2.772438e+000 4.890769e+000 2.496000e+001 vertex -2.407443e+000 -6.689721e+000 1.747200e+001 facet normal -3.469823e-16 -4.151400e-15 1.000000e+00 facet normal -0.550857 -0.679089 0.485175 facet normal -0.956957 -0.288281 0.0335834 vertex -5.38893 -1.02637 21.833.
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