(JEDEC MS-013AD, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_wide-rw/RI_20_1.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py. Vertex 7.3432 0.499373 6.98393. Placement saw_out = [h_margin . Gates. Variable step count, 1-10 steps possible. Wiring SW15 (once/stop) and cascade out. New Pull Request
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