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1.149903e+01 vertex -1.053382e+02 9.715134e+01 1.123243e+01 vertex -1.052763e+02 9.725134e+01 1.115112e+01 facet normal 0.787396 -0.189041 0.586746 facet normal 8.715000e-002 3.880221e-004 9.961951e-001 vertex -5.259008e+000 -6.506956e-002 2.495526e+001 facet normal 0.174179 -0.420511 0.890411 vertex 3.21772 -1.18228 19.1916 facet normal -0.173186 -0.0921987 0.980564 facet normal -0.554754 0.0419816 0.830954 vertex -7.31983 -0.636408 7.07423 facet normal -0.423073 -0.690391 0.58683 vertex 2.96974 -1.96858 19.8418 vertex 3.64807 2.3142 19.8418 vertex 3.63499 -2.35444 19.9 facet normal -0.76827 -0.629653 0.115322 facet normal 0.876744 0.468627 0.108209 vertex 5.71086 -1.13596 21.335 facet normal 0.97743 -0.186453 0.0993255 facet normal 8.456261e-02 -2.365524e-03 -9.964154e-01 facet normal 0.471711 0.881672 -0.0119957 facet normal -0.338901 0.181148 0.923218 facet normal -5.418452e-01 -6.316620e-03 8.404546e-01 facet normal 1.087114e-001 4.842103e-004 9.940732e-001 vertex -4.214520e+000 1.590398e+000 2.495526e+001 facet normal -0.243766 -0.29707 0.923216 vertex -8.96712 1.78367 3.76384 vertex -8.81405 -1.79875 3.82299 facet normal 9.369221e-001 3.100829e-003 3.495245e-001 vertex 4.042035e+000 1.627162e+000 2.475471e+001 facet normal 0.703593 -0.707111 0.0703601 facet normal -0.061823 -0.114014 0.991554 facet normal -1.011997e-14 5.429241e-15 -1.000000e+00 d8eca8dc7e Go to file 5e32fb4fc0 Change transistor footprint to inline_wide, fix DRC ground plane 56529bef3a0c7d0b31cfccd6b6ce971fb35b4e9c Updates from real TL0x4, fix pots being backwards, tighten up schematic, fit letter instead of A4 Add note resulting from real TL0x4s d12ec1f19bbae8f01395e4c76a152d3d4ce7a3d4 created pull request 'Fix rail clearance = ~11.675mm.

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