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Back2021 07:48:29 PM EDT Generated from schematic by Eeschema 5.1.9-73d0e3b20d~88~ubuntu20.04.1 Generated from schematic into main v1 Final tweaks, version submitted to JLCPCB on 20240124 Final.
- 0.0926003 0.995036 vertex 2.47665.
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- TSSOP, 50 Pin (JEDEC MS-013AC, https://www.analog.com/media/en/package-pcb-resources/package/233848rw_20.pdf), generated with.
- Pots: barely enough to attach.