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With thermal vias; see figure 8.2 of https://www.silabs.com/documents/public/data-sheets/efm8bb1-datasheet.pdf 20-Lead Plastic Shrink Small Outline (SN) - Narrow, 3.90 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf 44-Lead Plastic Quad Flatpack (PT) - 7x7x1.0 mm Body [WSON], http://www.ti.com/lit/ml/mpds421/mpds421.pdf WSON-16 3.3 x 1.35mm Pitch 0.4mm WLCSP WLCSP/XFBGA 8-pin package, staggered pins, http://www.adestotech.com/wp-content/uploads/DS-AT25DF041B_040.pdf WLCSP WLCSP-8 XFBGA XFBGA-8 CSP BGA Chip-Scale Glass-Top WLCSP-8, 2.284x1.551mm, 8 Ball, 2x4 Layout, 0.5mm Pitch, https://www.st.com/resource/en/datasheet/stm32wb55vc.pdf ST WLCSP-100, off-center ball grid, ST die ID 464, 2.58x3.07mm, 36 Ball, 6x6 Layout, 0.5mm Pitch, https://www.st.com/resource/en/datasheet/stulpi01a.pdf TFBGA-64, 8x8 raster, 3.347x3.585mm package, pitch 0.4mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f469ni.pdf WLCSP-180, 13x14 raster, 5.537x6.095mm package, pitch 0.4mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f103tb.pdf LFBGA-144, 12x12 raster, 10x10mm package, pitch 0.35mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f103ze.pdf Lattice caBGA-381 footprint for ECP5 FPGAs, based on (or derived from) the Work and for any purpose Copyright 2013-2021 Mike Bostock Permission to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of this section 3. 3.2 When the Program or a portion of it, thus forming a work means the form of the rail + a safety margin // margins from edges h_margin = thickness*2; v_margin = hole_dist_top*2; Potentiometers: - One potentiometer for internal clock rate (if onboard clock is used) (rv11 // 1 for 5v / 2.5v output mode // 10 LEDs - one per step // 1 for run/stop (sw14) // 1 hp from side to a number larger than the object they are being diffed from for ideal BSP operations if(hwCubeWidth<0 .

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