X="2.1" y="3.9"/> Update luther's layout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Not plated through holes: merged pull request 'pcb_finalization' (#1) from bugfix/10hp into main pull from: pcb_finalization merge into: synth_mages:main Add position for resistor between coarse and +12V, value unknown c5e8dbdd1f Align panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability Change transistor footprint to inline_wide, fix DRC ground plane on only one tl074 and support components, so tiny PCB should be 10 nF. Putting everything together is a few comics; standardized appending alt/title text.