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Back'track'" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 0 Minor layout tweaks.
- 0.768773 0.108219 facet normal -4.050582e-01 9.142909e-01.
- RK09D Single Snapin 113004U 1130A6S 11300DR 1130A8G 1130081.
- Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alpha_16mm_Long_Pin_Single_Vertical.kicad_mod Normal file View.