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ID 482, 4.2x3.95mm, 90 Ball, X-staggered 7x5 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32wb15cc.pdf#page=119 ST WLCSP-52, ST die ID 471, 4.437x4.456mm, 100 Ball, 10x10 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32g051f8.pdf#page=102 ST WLCSP-25, ST die ID 456, 1.94x2.4mm, 20 Ball, 4x5 Layout, 0.4mm Pitch, https://www.nxp.com/docs/en/package-information/SOT1963-1.pdf ST LFBGA-354, 16.0x16.0mm, 354 Ball, 19x19 Layout, 0.5mm Pitch, https://www.ti.com/lit/ds/symlink/dac80508.pdf Analog LFCSP, 16 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/436412f.pdf#page=22), generated with kicad-footprint-generator JST XH series connector, B04B-XASK-1-A (http://www.jst-mfg.com/product/pdf/eng/eXA1.pdf), generated with kicad-footprint-generator JST XH series connector, 53398-1571 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator JST PUD series connector, 14111113001xxx (https://b2b.harting.com/files/download/PRD/PDF_TS/1411XX13001XXX_100228421DRW046C.pdf), generated with kicad-footprint-generator JST SH series connector, S02B-XASK-1N-BN (http://www.jst-mfg.com/product/pdf/eng/eXA1.pdf), generated with kicad-footprint-generator Soldered wire connection, for 5 times 0.75 mm² wires, reinforced insulation, conductor diameter 0.4mm, outer diameter 1.5mm, size source Multi-Contact FLEXI-E 0.15 (https://ec.staubli.com/AcroFiles/Catalogues/TM_Cab-Main-11014119_(en)_hi.pdf), bend radius 3 times outer diameter, generated with kicad-footprint-generator Molex 734 Male header (for PCBs); Straight solder pin 1 https://www.wolfspeed.com/media/downloads/87/CSD01060.pdf TO-252 / DPAK SMD package, tab to pin 1 x 1 mm, 734-164 , 4 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator Molex MicroClasp Wire-to-Board System, 55935-0510, with PCB trace layout created pull request 'pcb_finalization' (#1) from pcb_finalization into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/4 Merge pull request 'new_footprints' (#5) from new_footprints into main v1 Final tweaks, version submitted to JLCPCB on 20240124 63579cf959 Add notes about wiring SW15 cross-board Add design rules for jlcpcb 4ee6887723 Add some perfboard sections, power headers, teardrops checkpoint before getting really weird with WireIt A couple more minor clearance tweaks Add ground fills, fix some clearance issues, make all power traces large Added input resistor for sync; placed everything on PCB with on-board components Added hard sync to schematic, laid out PCB with on-board components Added hard sync (to a clock/gate/trigger input) Quantizer Interfaces to digital components and interconnects between middle and bottom railHeight.

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