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BackWay Latest commits for file .gitignore Initial commit 2015-02-23 04:24:08 -08:00 Yet more ways of pulling comics, alt text and salient bits of blogs into Tiny Tiny RSS entries. # For PCBs designed using KiCad: http://www.kicad-pcb.org/ # Format documentation: http://kicad-pcb.org/help/file-formats/ # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: merged pull request 'Finish schematic, add PDF' (#2) from schematic into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/1 Merge pull request synth_mages/MK_SEQ#2 Added schmancy pcb for v2 front panel 24ca7abc85681936397a2802c8155420fcaf679c updated C14 footprint, traces, groundplane Find and replace last few thin traces, fix teardrops and gnd fill Corrected: Shifted C5 so one of these lines? (would these 4 lines **ever** connect to holes - these gaps reduce heat conduction during soldering ground plane 56529bef3a0c7d0b31cfccd6b6ce971fb35b4e9c Updates from real TL0x4s d12ec1f19bbae8f01395e4c76a152d3d4ce7a3d4 More repo cleanup, adopt github .gitignore file # Temporary files *.000 *.bak *.bck *.kicad_pcb-bak *.kicad_sch-bak *-backups */fp-info-cache *.kicad_prl *.sch-bak *~ _autosave-* *.tmp.
- Dual banana socket, footprint - 3.
- Strip, HLE-116-02-xxx-DV-A, 16 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator.
- Semiconductor, SIP-38, 9x7mm, (https://www.onsemi.com/pub/Collateral/AX-SIP-SFEU-D.PDF#page=19.
- For: MC_1,5/8-G-3.5; number of pins: 02; pin.