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481 .../PCB/precadsr_Gerbers/precadsr-B_Paste.gbr | 15 .../precadsr-panel-PasteTop.gtp | 15 .../precadsr-panel-SilkBottom.gbo | 799 .../precadsr-panel-drl_map.pdf | Bin 0 -> 38860 bytes Panels/futura medium condensed bt.ttf' Delete 'Panels/futura medium bt.ttf' From abc34915f3e0cdda969d62254e292cd8631b805a Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add PSU Latest commits for branch v1.1 Finish PCBs Checkpoint after tweaking footprints some more, starting over at 14hp Added hard sync to schematic, laid out PCB with on-board components PCB initial layout, no traces "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, PCB initial layout, no traces "solder_mask_clearance": 0.0, PCB initial layout, no traces "solder_mask_clearance": 0.0, PCB initial layout, no traces "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, PCB initial layout, no traces Initial kicad, images, gitignore for kicad backups *-backups More repo cleanup, adopt github .gitignore file # Temporary files fp-info-cache # Netlist files (exported from Pcbnew *.ses # Exported BOM files All-in-one module with a wire. 06850ab678 Delete '3D Printing/Panels/AD&D 1e spell names in Filmoscope Quentin/Panels/FIREBALL VCO.png' 811ef45c76 schematic start, and some example modules main 5a4e89eea6 Add position for resistor between coarse and +12V, value unknown Add position for resistor between coarse and +12V, value unknown .. Fireball VCO saw wave core.circuitjs.txt Latest commits for file Panels/FIREBALL VCO.png | Bin 0 -> 12724 bytes .../Panels/POLYMORPH.png | Bin 0 -> 163520 bytes Images/IMG_6777.JPG | Bin 0 -> 149061 bytes Images/IMG_6770.JPG | Bin 0 -> 12724 bytes .../POLYMORPH.png | Bin 11692 -> 0 bytes From 2bb058d5715f395d3571ea05d3008566787a2bdb Mon Sep 17 00:00:00 2001 Subject: [PATCH] glide fix a5c5ff12ce18fecaaf346f973863d12bf361ac82 Notes from MK's PCB livestream 3afa35e4b1 PCB initial layout, no traces "solder_mask_clearance": 0.0, PCB initial layout, no traces.

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