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Ref="S2" Part="1" AR Path="/607ED812/60C3833D" Ref="R21" Part="1" AR Path="/60A9C081" Ref="R?" Part="1" AR Path="/607ED812/60C3833D" Ref="R21" Part="1" AR Path="/607ED812/60A9C096" Ref="R24" Part="1" AR Path="/60A9C096" Ref="R?" Part="1" AR Path="/607ED812/60A9C088" Ref="R30" Part="1" AR Path="/607ED812/60C38349" Ref="R10" Part="1" AR Path="/60802BB2" Ref="R?" Part="1" AR Path="/607ED812/60800A40" Ref="R113" Part="1" AR Path="/607ED812/60800A40" Ref="R27" Part="1" AR Path="/60A9C0A9" Ref="R?" Part="1" AR Path="/607ED812/60A9C081" Ref="R26" Part="1" AR Path="/607ED812/60C3833D" Ref="R8" Part="1" AR Path="/60C38349" Ref="R?" Part="1" AR Path="/607ED812/6091D1B4" Ref="S2" Part="1" AR Path="/60A9C096" Ref="R?" Part="1" AR Path="/607ED812/60A9C088" Ref="R14" Part="1" AR Path="/60800A40" Ref="R?" Part="1" AR Path="/607ED812/609384DB" Ref="#FLG0102" Part="1" AR Path="/607ED812/60802BB2" Ref="R114" Part="1" AR Path="/607ED812/60C38343" Ref="R22" Part="1.

• Normal -7.748055e-001 6.321996e-001 0.000000e+000.
• 0.65 exposed pad (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-20-32/ Infineon SO.
• */ left_rib_x = thickness + 6 .

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