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Module v_wall(h, l, wall_thickness); Align panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability Change transistor footprint to inline_wide, fix DRC ground plane 56529bef3a0c7d0b31cfccd6b6ce971fb35b4e9c Updates from real TL0x4, fix pots being backwards, tighten up schematic, fit letter instead of A4 d8eca8dc7e Add note resulting from real TL0x4s 5cacbfea2e Add polygon calculation for wing plates 3e868f13c4 Go to file 99b8f1493d More layout.

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