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Unit Outputs ±12V DC, +5V DC, and passes CV and trigger or gate per step. (10 - One potentiometer for internal clock rate. One SPDT switch to set output voltages. (10) One potentiometer per step, to enable/disable gate per step. (10 One potentiometer for internal clock rate. Arrasta Playbook REP: repique MSD: mid surdo (sometimes MS1, MS2, etc, if multiple measures or variations BSD: back surdo (L for low, H for high) R/L: accented note (right/left hand suggested r/l Quieter, unaccented note * A trill, generally three very fast notes on updating the fireball for rev 2 beta d89db83df13552281151487e636d3175f5aa0e7b updates to rev 2 beta edits README.md file edits README.md file - Before producing, confirm footprint dimensions for capacitors, diodes (inc. LEDs), and barrel power jack.

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