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"Layer B.Mask" "Notes": "Layer F.Mask" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer B.Paste" "Notes": "Layer F.Mask" "Notes": "Layer B.Mask" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Thu Aug 12 11:11:04 2021 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add schematic, start on PCB with exploratory 8hp layout 0d370a24cdcaf6d3fd7f0316855522b79df0fe9a 3583986e89 Finished PCB, passes all passable DRCs Show-stopping bugs needing bodges: Errant connection between R25 and R1. This needs to be centered around the outer circumference of the set screw hole's center over the base panel's thickness to account for squishing width = 38; // [1:1:84] width = 24; // [1:1:84] /* [Holes] */ hole_dist_top = 2.5; // margins from edges v_margin = hole_dist_top*2 + thickness; width_mm = hp_mm(width); // where to put reinforcing walls; i.e. The thickness of the indenting cones. Cone_indents_count = 7; // generally-useful spacing amount for vertical columns of stuff col_left = thickness * 2; right_rib_x = width_mm - thickness*2; From 88bf85725f2c856b6f99f99568e61e08e1060d3b Mon Sep 17 00:00:00 2001 Subject: [PATCH] adds ideas for a single 1 mm² wire, basic insulation, conductor diameter 1.25mm, outer diameter 2mm, size source Multi-Contact FLEXI-E 1.5 (https://ec.staubli.com/AcroFiles/Catalogues/TM_Cab-Main-11014119_(en)_hi.pdf), bend radius 3 times outer diameter, generated with kicad-footprint-generator Molex.

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