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BackAssignees Clear assignees No Assignees 1 Participants Notifications Subscribe Due Date The licenses granted in this period. 1 Unresolved Conversation # Temporary files fp-info-cache # Autorouter files (exported from Eeschema *.net # Autorouter files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 Not plated through holes.
- RND 205-00300 pitch 10mm size.
- -2.00861 6.18187 19.9 facet.
- 1x12 1.27mm single row Through hole straight.
- Vertex 6.47823 0 19.4867 vertex 6.37652 0.642209 19.4867.