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BackFile c4e1c30b9b Add jlc constraints DRC; replace order number text Fireball/Fireball_panel.kicad_pcb | 3 | A1M | Potentiometer | | | | | J8 | 1 uF | Unpolarized capacitor | | | | J4 | 1 | | | | | | | | C2, C5, C6, C8, C9 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10 | 8 "active_layer_preset": "All Copper Layers", re-re-remove the mysterious extra trace re-re-remove the mysterious extra trace Add notes about wiring SW15 cross-board Add design rules for jlcpcb 9360e76802 Add design rules for jlcpcb Add design rules for jlcpcb Latest commits for file Panels/10_step_seq.scad Experimenting with more panel layout } Experimenting with more panel layout Start of LM13700 version to see why Start of LM13700 version to see why 969311f00cbb6d6ece9a25b5fb1d4e2884e468c0 Assorted updates More SR1 notation main master PSU/Synth Mages Power Word Stun.kicad_pro Add scad for v3.2 Add scad for v3.2 From 5aaea69ed6fde3a14d8431b95cdb61f2e99d3f78 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Move LED resistors From d81094c64ef3dbd9cdcdc0341bc85fcc9deb080e Mon Sep 17 00:00:00 2001 Subject: [PATCH] Update Schematics/schematic_bugs_v1.md Clock POT is too small for film; is film needed? - Smaller cap (476nF?) for C1 Ceramic 104s for C10, C14, might be fine, might introduce intermittents From c96644890cf0985bb0d02bb542ef75a0a00d53f2 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Use THT electrolytics, finish SMT layout, try on quentin font Schematics/Enlarge/Enlarge.kicad_prl | 10 uF tantalum\nMFOS 1, 1+15 electrolytic\n1 uF tanty looks better than EL\n(higher output, less leakage)\nbut only by a Contributor.
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