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Back# LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: merged pull request 'Fix rail clearance issues, make all power traces large main VCA/Schematics/Dual_VCA_with_cv2.diy 8684 lines master PSU/Synth Mages Power Word Stun Panel.kicad_pro Normal file Unescape
- 8.302385e-001 2.751038e-001 facet normal -6.797471e-001 -3.260837e-003 7.334393e-001.
- -7.425920e-001 6.697441e-001 0.000000e+000 vertex -9.918118e-002 5.624815e+000.