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BackFireball/Fireball.kicad_pro Latest commits for file Images/precadsr-panel-holes.png 972d8b1e07 adds front panel design and includes 2.5mm centerward shift for input and output jacks adds front panel and pcb into different files Add a front-panel PCB "net_color_mode": 1, "opacity": { More tweaks after pro review }, "pcbnew": { "last_paths": { "gencad": "", "idf": "", "netlist": "", "specctra_dsn": "", "step": "", "vrml": "" }, "page_layout_descr_file": "" }, "page_layout_descr_file": "" }, "page_layout_descr_file": "" }, "schematic": { "annotate_start_num": 0, "drawing": { More tweaks after pro review "different_unit_footprint": "error", "different_unit_net": "error", "duplicate_reference": "error", "duplicate_sheet_names": "error", More tweaks after pro review Apply jlcpcb's design rules, small fixes for those 7022ad9ddb couple more minor clearance tweaks Subject: [PATCH 18/18] Final revision; added custom DRC as project file tstamp 1c9c2c29-57db-4a4e-bbff-29f893ea0430) Final revision; added custom DRC as project file Final revision; added custom DRC as project file tstamp 30cbcf99-eb70-4e15-8409-33e0ecd46602) Final revision; added custom DRC as project file version 1) #Kicad 7 # 2-layer, 1oz copper condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'" condition "A.Type == 'track' && B.Type == 'track'" (condition "A.isPlated() && B.Type == A.Type && A.Net != B.Net" condition "A.Pad_Type == 'NPTH, mechanical' .
- 0.272942 0.961292 vertex -0.0610838 7.13918 6.87866 vertex 6.9298.
- SPT 2.5/12-H-5.0 1991079 Connector Phoenix.
- 3.165253e+000 2.494118e+001 facet normal 1.284292e-001 2.247510e-001.
- -6.71529 -0.463226 7.17947 vertex 5.11681 -4.57918 7.04537.