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BackBin 69774 -> 0 bytes From b2f0340111348a8deafde0ffe244939fe4eeb6b7 Mon Sep 17 00:00:00 2001 Subject: [PATCH 01/13] initial notes for v1 front panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability Change transistor footprint to inline_wide, fix DRC ground plane 56529bef3a0c7d0b31cfccd6b6ce971fb35b4e9c Updates from real TL0x4s 5cacbfea2e Add polygon calculation for wing plates Add VCA shaek layout Adding SynthMages footprint library Notes from debugging Clock POT is too small; need more than 100k to get 1:1 between schematic and PCB, no warnings More work finding space for everything, lining things up more c5efc87d8e Make slider and LED footprints match current OpenSCAD model Checkpoint after converting most things to SMD 55ee65a5e94ad245f04db09ef472959294e7cca0 Still trying to implement chaining Checkpoint before trying to add picture Schematics/{schematic_bugs_v1.txt => schematic_bugs_v1.md} | 3 | 10k | Resistor | | J3, J4, J5 | 3 | AudioJack2 | Audio Jack, 2 Poles (Mono / TS), Switched T Pole (Normalling)"/>