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PCBs designed using KiCad: http://www.kicad-pcb.org/ # Format documentation: http://kicad-pcb.org/help/file-formats/ # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Update luther's layout Update luther's layout 10k NTC Thermistor Vishay HVMDIP HEXDIP DirectFET L4 MOSFET.

  • -5.25446 -1.11698 22.0001 vertex -1.11698 5.25446 22.0001 vertex.
  • -0.288805 0.952403 0.0975683 vertex -3.44415 -8.31492 3.
  • TDK, MLZ2012_h1.25mm, 2.0x1.25x1.25mm, "https://product.tdk.com/system/files/dam/doc/product/inductor/inductor/smd/catalog/inductor_commercial_decoupling_mlz2012_en.pdf" Inductor,TDK, VLS-6045.
  • For: MSTB_2,5/9-GF; number of pins: 13; pin pitch.
  • New Pull Request